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PRELIMINARY
GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT
FEATURES
* * * * * * * * * * * * * * * Zero Bus Latency, no dead cycles between write and read cycles Fast clock speed: 200, 166, 133, and 100MHz Fast access time: 3.2, 3.6, 4.2, 5.0ns Internally synchronized registered outputs eliminate the need to control OE# Single 3.3V -5% and +5% power supply VCC Separate VCCQ for 3.3V or 2.5V I/O Single R/W# (READ/WRITE) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear 4-word burst capability Individual byte write (BWa# - BWd#) control (may be tied LOW) CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion SNOOZE MODE for low power standby JTAG boundary scan Low profile 119 bump, 14mm x 22mm PBGA (Ball Grid Array) and 100 pin TQFP packages
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
256K x 36 SRAM 512K x 18 SRAM
+3.3V SUPPLY, +3.3V or +2.5V I/O
polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (CE#, CE2# and CE2), cycle start input (ADV/LD#), clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#), and read-write control (R/W#). BWc# and BWd# apply to GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either read or write. A clock enable (CKE#) pin allows operation of the GVT71256ZC36/GVT71512ZC18 to be suspended as long as necessary. All synchronous inputs are ignored when (CKE#) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE#, CE2, CE2#) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD# is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high impedance state two cycles after chip is deselected or a write cycle is initiated. The GVT71256ZC36 and GVT71512ZC18 have an onchip 2-bit burst counter. In the burst mode, the GVT71256ZC36 and GVT71512ZC18 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD# signal is used to load a new external address (ADV/LD#=LOW) or increment the internal burst counter (ADV/LD#=HIGH) Output enable (OE#), snooze enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE# can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.
Galvantech, Inc. reserves the right to chang e products or specifications without notice .
OPTIONS
* Timing 5.0ns cycle/3.2ns access 6.0ns cycle/3.6ns access 7.5ns cycle/4.2ns access 10ns cycle/5.0ns access Package Versions 119-bump PBGA 100-pin TQFP
MARKING
-5 -6 -7.5 -10 B T
*
GENERAL DESCRIPTIO N
The GVT71256ZC36 and GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144x36 and 524,288x18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Galvantech Synchronous Burst SRAM family employs highspeed, low power CMOS designs using advanced triple-layer
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
ZZ MODE CKE# ADV/LD# R/W# BWa#, BWb# BWc#, BWd# CE#, CE2#, CE2 SA0, SA1, SA
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
256K X 36 FUNCTIONAL BLOCK DIAGRAM
256K x 9 x 4 SRAM Array
Address
Control
Control Logic
Mux
CLK
Output Registers
OE#
Output Buffers
DQa-DQd
512K X 18 FUNCTIONAL BLOCK DIAGRAM
ZZ MODE CKE# ADV/LD# R/W# BWa#, BWb# CE#, CE2#, CE2 SA0, SA1, SA 512K x 9 x 2 SRAM Array
Address
Control
Control Logic
Mux
CLK
Output Registers
OE#
Output Buffers
DQa, DQb
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
May 22, 199 9
2
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
DO Sel
DI
Input Registers
DO Sel
DI
Input Registers
PRELIMINARY
GALVANTECH, INC.
256Kx36, 119-Bump PBGA (Top View)
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 SA CE2 SA DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd SA NC TMS 3 SA SA SA VSS VSS VSS BWc# VSS NC VSS BWd# VSS VSS VSS MODE SA TDI 4 NC ADV/LD# VCC NC CE# OE# SA R/W# VCC CLK NC CKE# SA1 SA0 VCC SA TCK 5 SA SA SA VSS VSS VSS BWb# VSS NC VSS BWa# VSS VSS VSS VCC SA TDO 6 SA CE2# SA DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa SA NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
256Kx36, 100-PIN TQFP (Top View)
SA SA CE# CE2 BWd# BWc# BWb# BWa# CE2# VCC VSS CLK R/W# CKE# OE# ADV/LD# NC SA SA SA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc VCC VCC VCC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS VCC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIN DESCRIPTION S
256Kx36 TQFP PIN S
37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 93, 94, 95, 96
256Kx36 PBGA PIN S
4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 3T, 4T, 5T 5L 5G 3G 3L
SYMBOL
SA0, SA1, SA
TYPE
InputSynchronous
Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD# LOW, CKE# LOW and true chip enables. SA0 and SA1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. Synchronous Byte Write Enables: Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W# and ADV/LD# are sampled LOW), the appropriate byte write signal (BWx#) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when R/W# is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins. BWx# can all be tied LOW if always doing write to the entire 36-bit word. Synchronous Clock Enable Input: When CKE# is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CKE# sampled HIGH on the device outputs is as if the low to high clock transition did not occur. For normal operation, CKE# must be sampled LOW at rising edge of clock. Read Write: R/W# signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD# is a Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later.
BWa#, BWb#, BWc#, BWd#
InputSynchronous
87
4M
CKE#
InputSynchronous
88
4H
R/W#
InputSynchronous
May 22, 199 9
3
Rev. 5/99
MODE SA SA SA SA SA1 SA0 TMS TDI VSS VCC TDO TCK SA SA SA SA SA SA SA
TOP VIEW 119 LEAD BGA
DESCRIPTIO N
Galvantech, Inc. reserves the right to change products or specifications without notice .
PRELIMINARY
GALVANTECH, INC.
PIN DESCRIPTIONS (continued )
256Kx36 TQFP PIN S
89 98, 92
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
256Kx36 PBGA PIN S
4K 4E, 6B
SYMBOL
CLK CE#, CE2#
TYPE
InputSynchronous InputSynchronous
DESCRIPTIO N
Clock: This is the clock input to GVT71256ZC36. Except for OE#, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK . Synchronous Active Low Chip Enable: CE# and CE2# are used with CE2 to enable the GVT71256ZC36. CE# or CE2# sampled HIGH or CE2 sampled LOW, along with ADV/LD# LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be HIGH-Z two clock cycles after chip deselect is initiated . Synchronous Active High Chip enable: CE2 is used with CE# and CE2# to enable the chip. CE2 has inverted polarity but otherwise is identical to CE# and CE2# . Asynchronous Output Enable: OE# must be LOW to read data. When OE# is HIGH, the I/O pins are in high impedance state. OE# does not need to be actively controlled for read and write cycles. In normal operation, OE# can be tied LOW . Advance/Load: ADV/LD# is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD# is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and R/W# are ignored when ADV/LD# is sampled HIGH . Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input.
97 86
2B 4F
CE2 OE#
inputSynchronous Input
85
4B
ADV/LD#
InputSynchronous
31
3R
MODE
InputStatic
64
7T
ZZ DQa DQb DQc DQd
InputSnooze Enable: This active HIGH input puts the device in low power consumption Asynchronous standby mode. For normal operation, this input has to be either LOW or NC . Input/ Output Data Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins .
51, 52, 53, 56-59, 62, 63 (a) 6P, 7P, 7N, 6N, 6M, 68, 69, 72-75, 78, 79, 80 6L, 7L, 6K, 7K, 1, 2, 3, 6-9, 12, 13 (b) 7H, 6H, 7G, 6G, 6F, 18, 19, 22-25, 28, 29, 30 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 38 39 43 42 14, 15, 16, 41, 65, 66, 91 2U 3U 4U 5U 4C, 2J, 4J, 6J, 4R, 5R
TMS TDI TCK TDO VCC VSS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If SERIAL BOUNDARY SCAN (JTAG) is not used, these pins can be floating (i.e. No Connect) or be connected to VCC .
Output Supply Ground
IEEE 1149.1 test output. LVTTL-level output. If SERIAL BOUNDARY SCAN (JTAG) is not used, these pins can be floating (i.e. No Connect) . Power Supply: +3.3V -5% and +5%. Ground: GND.
5, 10, 17, 21, 26, 40, 55, 3D, 5D, 3E, 5E, 3F, 5F, 60, 67, 71, 76, 90 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P 4, 11, 20, 27, 54, 61, 70, 77 84 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 7R, 1T, 2T, 6T, 6U
VCCQ NC
I/O Supply -
Output Buffer Supply: +3.3V -0.165V and +0.165V for 3.3V I/O. +2.5V -0.125V and +0.4V for 2.5V I/O. No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND.
May 22, 199 9
4
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
512Kx18, 119-Bump PBGA (Top View)
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQb NC VCCQ NC DQb VCCQ NC DQb VCCQ DQb NC NC NC VCCQ 2 SA CE2 SA NC DQb NC DQb NC VCC DQb NC DQb NC DQb SA SA TMS 3 SA SA SA VSS VSS VSS BWb# VSS NC VSS VSS VSS VSS VSS MODE SA TDI 4 NC ADV/LD# VCC NC CE# OE# SA R/W# VCC CLK NC CKE# SA1 SA0 VCC NC TCK 5 SA SA SA VSS VSS VSS VSS VSS NC VSS BWa# VSS VSS VSS VCC SA TDO 6 SA CE2# SA DQa NC DQa NC DQa VCC NC DQa NC DQa NC SA SA NC 7 VCCQ NC NC NC DQa VCCQ DQa NC VCCQ DQa NC VCCQ NC DQa NC ZZ VCCQ
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
512Kx18, 100-PIN TQFP (Top View)
SA SA CE# CE2 NC NC BWb# BWa# CE2# VCC VSS CLK R/W# CKE# OE# ADV/LD# NC SA SA SA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb VCC VCC VCC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS VCC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TOP VIEW 119 LEAD BGA
PIN DESCRIPTION S
512Kx18 TQFP PIN S
37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 93, 94,
512Kx18 PBGA PIN S
4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T 5L 3G
SYMBOL
SA0, SA1, SA
TYPE
InputSynchronous
Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD# LOW, CKE# LOW and true chip enables. SA0 and SA1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. Synchronous Byte Write Enables: Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W# and ADV/LD# are sampled LOW), the appropriate byte write signal (BWx#) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when R/W# is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BWa# controls DQa pins; BWb# controls DQb pins. BWx# can all be tied LOW if always doing write to the entire 18-bit word . Synchronous Clock Enable Input: When CKE# is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CKE# sampled HIGH on the device outputs is as if the low to high clock transition did not occur. For normal operation, CKE# must be sampled LOW at rising edge of clock. Read Write: R/W# signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD# is a Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later.
BWa#, BWb#
InputSynchronous
87
4M
CKE#
InputSynchronous
88
4H
R/W#
InputSynchronous
May 22, 199 9
5
Rev. 5/99
MODE SA SA SA SA SA1 SA0 TMS TDI VSS VCC TDO TCK SA SA SA SA SA SA SA
DESCRIPTIO N
Galvantech, Inc. reserves the right to change products or specifications without notice .
PRELIMINARY
GALVANTECH, INC.
PIN DESCRIPTIONS (continued )
512Kx18 TQFP PIN S
89 98, 92
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
512Kx18 PBGA PIN S
4K 4E, 6B
SYMBOL
CLK CE#, CE2#
TYPE
InputSynchronous InputSynchronous
DESCRIPTIO N
Clock: This is the clock input to GVT71512ZC18. Except for OE#, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK . Synchronous Active Low Chip Enable: CE# and CE2# are used with CE2 to enable the GVT71512ZC18. CE# or CE2# sampled HIGH or CE2 sampled LOW, along with ADV/LD# LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be HIGH-Z two clock cycles after chip deselect is initiated . Synchronous Active High Chip enable: CE2 is used with CE# and CE2# to enable the chip. CE2 has inverted polarity but otherwise is identical to CE# and CE2# . Asynchronous Output Enable: OE# must be LOW to read data. When OE# is HIGH, the I/O pins are in high impedance state. OE# does not need to be actively controlled for read and write cycles. In normal operation, OE# can be tied LOW . Advance/Load: ADV/LD# is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD# is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and R/W# are ignored when ADV/LD# is sampled HIGH . Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input.
97 86
2B 4F
CE2 OE#
inputSynchronous Input
85
4B
ADV/LD#
InputSynchronous
31
3R
MODE
InputStatic
64 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 38 39 43 42 14, 15, 16, 41, 65, 66, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 84, 95, 96
7T
ZZ DQa DQb
InputSnooze Enable: This active HIGH input puts the device in low power consumption Asynchronous standby mode. For normal operation, this input has to be either LOW or NC . Input/ Output Data Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Byte "a" is DQa pins; Byte "b" is DQb pins .
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2 P
2U 3U 4U 5U 4C, 2J, 4J, 6J, 4R, 5R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
TMS TDI TCK TDO VCC VSS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If SERIAL BOUNDARY SCAN (JTAG) is not used, these pins can be floating (i.e. No Connect) or be connected to VCC . IEEE 1149.1 test output. LVTTL-level output. If SERIAL BOUNDARY SCAN (JTAG) is not used, these pins can be floating (i.e. No Connect) . Power Supply: +3.3V -5% and +5%. Ground: GND.
Output Supply Ground
VCCQ NC
I/O Supply -
Output Buffer Supply: +3.3V -0.165V and +0.165V for 3.3V I/O. +2.5V -0.125V and +0.4V for 2.5V I/O. No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND.
PARTIAL TRUTH TABLE FOR READ/WRIT E1
FUNCTIO N R/W# BWa# BWb# X H H L H H L BWc# X H H H L H L BWd# X H H H H L L
Read H X No Write L H Write Byte a (DQa)2 L L Write Byte b (DQb)2 L H Write Byte c (DQc)2 L H Write Byte d (DQd}2 L H Write all bytes L L Note:1 1. L means logic LOW. H means logic HIGH. X means "Don't Care. "
2. 3.
Multiple bytes may be selected during the same cycle. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
6
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
First Address (external )
A...A00 A...A01 A...A10 A...A11
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or NC )
Second Address (internal )
A...A01 A...A00 A...A11 A...A10
Third Address (internal )
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal )1
A...A11 A...A10 A...A01 A...A00
LINEAR BURST ADDRESS TABLE (MODE = VSS )
First Address (external )
A...A00 A...A01 A...A10 A...A11
Second Address (internal )
A...A01 A...A10 A...A11 A...A00
Third Address (internal )
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal )1
A...A11 A...A00 A...A01 A...A10
Note: 1. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
FUNCTIONAL TIMING DIAGRA M
CYCLE CLOCK ADDRESS (SA0, SA1, SA) n+19 n+20 n+21 n+22 n+23 n+24 n+25 n+26 n+27
A19
A20
A21
A22
A23
A24
A25
A26
A27
CONTROL (R/W#, BWx#, ADV/LD#)
C19
C20
C21
C22
C23
C24
C25
C26
C27
DATA DQ[a:d]
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
Note: 1. This assumes that CKE#, CE#, CE2 and CE2# are all True. 2. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data delay from the rising edge of clock. 3. DQc and DQd apply to 256Kx36 device only.
May 22, 199 9
7
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
TRUTH TABLE(1-9)
OPERATIO N
DESELECT CYCL E CONTINUE DESELECT/NO P READ CYCLE (BEGIN BURST ) READ CYCLE (CONTINUE BURST ) DUMMY READ (BEGIN BURST ) DUMMY READ (CONTINUE BURST ) WRITE CYCLE (BEGIN BURST ) WRITE CYCLE (CONTINUE BURST ) ABORT WRITE (BEGIN BURST ) ABORT WRITE (CONTINUE BURST ) IGNORE CLOCK EDGE /NOP
PREVIOUS CYCLE
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
ADDRESS USED X X External Next External Next External Next External Next X
R/W#
ADV/LD#
CE#
CKE#
BWx#
OE#
DQ (2 cycles later )
NOTES
X
DESELECT
X X H X H X L X L X X
L H L H L H L H L H H
H X L X L X L X L X X
L L L L L L L L L L H
X X X X X X L L H H X
X X X X H H X X X X X
High-Z High-Z Q Q High-Z High-Z D D High-Z High-Z 10 11 10, 11 12 10 11 10, 11 10
X READ X READ X WRITE X WRITE X
Note: 1. L means logic LOW. H means logic HIGH. X means "Don't Care. High-Z means HIGH IMPEDANCE. BWx# = L means " [BWa#*BWb#*BWc#*BWd#] equals LOW. BWx# = H means [BWa#*BWb#*BWc#*BWd#] equals HIGH. BWc# and BWd# apply to 256Kx36 device only. 2. CE# equals H means CE# and CE2# are LOW along with CE2 being HIGH. CE# equals L means CE# or CE2# is HIGH or CE2 is LOW.
CE# equals X means CE#, CE2# and CE2 are "Don't Care. "
3.
4. 5. 6. 7. 8. 9.
BWa# enables WRITE to byte "a" (DQa pins). BWb# enables WRITE to byte "b" (DQb pins). BWc# enables WRITE to byte "c" (DQc pins). BWd# enables WRITE to byte "d" (DQd pins). DQc, DQd, BWc# and BWd# apply to 256Kx36 device only. The device is not in SNOOZE MODE, i.e. the ZZ pin is LOW. During SNOOZE MODE, the ZZ pin is HIGH and all the address pins and control pins are "Don't Care." The SNOOZE MODE
can only be entered two cycles after the WRITE cycle, otherwise the WRITE cycle may not be completed .
All inputs, except OE#, ZZ and MODE pins, must meet setup time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge. OE# may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
Device outputs are ensured to be in High-Z during device power-up .
This device contains a 2-bit burst counter. The address counter is incremented for all CONTINUE BURST cycles. Address wraps to the initial address every fourth burst cycle. 10. CONTINUE BURST cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the R/W# control signal at the BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 11. DUMMY READ and ABORT WRITE cycles can be entered to setup subsequent READ or WRITE cycles or to increment the burst counter. 12. When an IGNORE CLOCK EDGE cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is WRITE or DESELECT cycle.
May 22, 199 9
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Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ............................................................2.0W Short Circuit Output Current ..........................................50mA
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability .
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S
(0oC
Ta 70C; VCC = 3.3V -5% and +5% unless otherwise noted)
CONDITION S
Data Inputs (DQxx ) All Other Input s
DESCRIPTIO N
Input High (Logic 1) Voltag e Input Low (Logic 0) Voltag e Input Leakage Curren t
SYMBO L
VIHD VIH VIl ILI ILI ILO VOH VOL VCC
MIN
2.0 2.0 -0.5 2.4 2.0
MAX
VCC+0.3 4.6 0.8 5 30 5
UNITS
V V V uA uA uA V V
NOTES
1,2 1,2 1, 2 6
0V < VIN < VCC
MODE and ZZ Input Leakage 0V < VIN < VCC Current Output Leakage Curren t Output High Voltag e Output Low Voltag e Supply Voltag e I/O Supply Voltag e 3.3V I/O 2.5V I/O Output(s) disabled, 0 V < VOUT < VCC IOH = -5.0mA for 3.3V I/ O IOH = -1.0mA for 2.5V I/ O IOL = 8.0mA
1 1 1 1 1 1
0.4 3.135 3.135 2.4 3.465 3.465 2.9
V V V V
VCCQ
DESCRIPTIO N
Power Supply Current: Operatin g CMOS Standb y
CONDITION S
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open, ADV/LD# = X, f = fMAX2 Device deselected; VCC = MAX ; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static ; VCC = MAX; CLK frequency = 0 Device deselected ; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
200
-5
560
-6
480
-7.5
410
-10
350
UNITS NOTES
mA 3, 4, 5, 7
ISB2
15
30
30
30
30
mA
4, 5, 7
TTL Standby
ISB3
20
50
50
50
50
mA
4, 5, 7
Clock Running
ISB4
50
230
200
190
170
mA
4, 5, 7
Note:
1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: VIH +6.0V for t t tKC /2 Undershoot: VIL -2.0V for t KC /2. Icc is given with no output current. Icc increases with greater output loading and faster cycle times . "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. Typical values are measured at 3.3V, 25oC and 20ns cycle time. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +50 A. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/CYC; f = 0 means no input lines are changing. t
May 22, 199 9
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Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 2) (0oC
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
TA 70oC; VCC = 3.3V -5% and +5%)
-5 200MHz
SYM MIN MAX
DESCRIPTIO N
Clock Clock cycle tim e Clock HIGH tim e Clock LOW tim e Output Times Clock to output vali d Clock to output invali d Clock to output in Low- Z Clock to output in High- Z OE to output vali d OE to output in Low- Z OE to output in High- Z Setup Times Address and Control s Data In Hold Times Address and Control s Data In
t t t t t t t t t t
-6 166MHz
MIN MAX
- 7.5 133MHz
MIN MAX
- 10 100MHz
MIN MAX UNITS NOTES
KC KH KL
5.0 1.8 1.8 3.2 1.0 1.0 1.0 0 3.5 1.5 1.5 0.5 0.5 3.0 3.2
6.0 2.1 2.1 3.6 1.0 1.0 1.0 0 3.5 1.5 1.5 0.5 0.5 3.0 3.6
7.5 2.6 2.6 4.2 1.0 1.0 1.0 0 3.5 1.8 1.8 0.5 0.5 3.0 4.2
10 3.5 3.5 5.0 1.0 1.0 1.0 0 3.5 2.0 2.0 0.5 0.5 3.0 5.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 3, 4 1, 3, 4 5 5 5 5 1, 3, 4 1, 3, 4
t
t
KQ
KQX
KQLZ OEQ
KQHZ
t
t
OELZ
OEHZ S
SD H
HD
CAPACITANCE
DESCRIPTIO N
Input Capacitanc e Input/Output Capacitance (DQ )
CONDITION S
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBO L
CI CO
TYP
4 7
MAX
4 6.5
UNITS
pF pF
NOTES
1 1
THERMAL CONSIDERATIO N
DESCRIPTIO N
Thermal Resistance - Junction to Ambien t Thermal Resistance - Junction to Cas e
CONDITION S
Still air, soldered on 4.25 x 1.125 inch 4-layer PC B
SYMBO L
JA JC
TQFP TY P
25 9
UNITS
o o
NOTES
C/W C/W
Note:
8. 9. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted .
10. Output loading is specified with CL=5pF as in Fig. 2 . 11. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 12. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined the in truth table. 13. Capacitance derating applies to capacitance different from theload capacitance shown in Fig. 1.
May 22, 199 9
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Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
AC TEST CONDITIONS FOR 3.3V I/O Input pulse levels Input rise and fall times Output rise and fall times(max) Input timing reference levels Output reference levels Output load 0V to 3.0V 1ns 1.8ns 1.5V 1.5V See Figures 1
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
OUTPUT LOADS FOR 3.3V I/O
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF
AC TEST CONDITIONS FOR 2.5V I/O Input pulse levels Input rise and fall times Output rise and fall times(max) Input timing reference levels Output reference levels Output load 0V to 2.5V 1ns 1.8ns 1.25V 1.25V See Figures 1A
Fig. 2 OUTPUT LOAD EQUIVALENT
OUTPUT LOADS FOR 2.5V I/O
DQ Z0 = 50 50 Vt = 1.25V
Fig. 1A OUTPUT LOAD EQUIVALENT
May 22, 199 9
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Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
READ TIMIN G
tKC
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
tKH tKL
CLK
tS tH
CKE#
tS tH
R/W#
tS tH
ADDRESS BWa#, BWb# BWc#, BWd#
A1
A2
tS
CE# (See Note)
tS
tH
tH
ADV/LD#
OE#
tKQLZ tKQ
Q(A1) Q(A2)
tKQX
Q(A2+1)
(CKE# HIGH, eliminates current L-H clock edge) Q(A2+2)
(Burst Wraps around to initial state) Q(A2+3) Q(A2)
tKQHZ
DQ
Pipeline Read
BURST PIPELINE READ Pipeline Read
Note: 1. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH . 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW . 4. R/W# is "Don't Care" when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM . 5. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
12
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
WRITE TIMIN G
tKC
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
tKH tKL
CLK
tS tH
CKE#
tS tH
R/W#
tS tH
ADDRESS BWa#, BWb# BWc#, BWd# CE# (See Note)
A1
tS
A2
tH
BW(A1)
tS
BW(A2)
BW(A2+1)
BW(A2+2)
BW(A2+3)
BW(A2)
tH
tS
tH
ADV/LD#
OE#
tSD tHD
D(A1) D(A2) D(A2+1) (CKE# HIGH, eliminates current L-H clock edge) D(A2+2) (Burst Wraps around to initial state) D(A2+3) D(A2)
DQ
Pipeline Write
Burst Pipeline Write Pipeline Write
Note: 1. D(A1) represents the first input to the external address A1. D( A2) represents the first input to the external address A2; D(A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input . 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH . 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW . 4. R/W# is "Don't Care" when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM . 5. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM . 6. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
13
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
tKC
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
READ/WRITE TIMIN G
tKH tKL
CLK
tS tH
CKE#
t
S
t
H
R/W#
tS tH
ADDRESS BWa#, BWb# BWc#, BWd#
A1
t
A2
S BW(A2)
tS t
A3
H
A4
BW(A4)
A5
BW(A5)
A6
A7
A8
A9
CE# (See Note)
t
tH
S
t
H
ADV/LD#
OE#
tKQ tKQHZ Q(A1) Read Read D(A2) Write Write D(A4) D(A5) tKQL
Z
tKQX Q(A6) Read Q(A7)
DATA Out (Q)
Q(A3)
DATA In (D)
Note:
1. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH . 3. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM . .4. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
14
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
CKE# TIMIN G
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
tKC t
t
KH
KL
CLK
tS tH
CKE#
tS tH
R/W#
tS tH
ADDRESS BWa#, BWb# BWc#, BWd#
A1
t
A2
S
tH
A3
A4
A5
t
S
CE# (See Note)
t
tH
S
tH
ADV/LD#
OE#
tKQ tKQHZ
DATA Out (Q)
tKQLZ
Q(A1)
tKQX tSD tHD
Q(A3)
DATA In (D)
D(A2)
Note:
1. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH . 3. CKE# when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state . 4. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM . 5. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
15
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
CE# TIMIN G
tKC
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
tKH tKL
CLK
tS tH
CKE#
tS tH
R/W#
tS tH
ADDRESS BWa#, BWb# BWc#, BWd#
A1
A2
tS
A3
tH
A4
A5
tS
CE# (See Note) ADV/LD#
tOEQ
tH
tS
tH
OE#
tOELZ tKQHZ tOEHZ
DATA Out (Q)
tKQLZ
Q(A1)
tKQ
Q(A2)
tKQX tSD tHD
Q(A4)
DATA In (D)
D(A3)
Note:
1. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc. 2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2# is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on this waveform, CE2 is HIGH . 3. When either one of the Chip enables (CE#, CE2 or CE2#) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z two cycles after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed . 4. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM . 5. BWc# and BWd# apply to 256Kx36 device only.
May 22, 199 9
16
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
OVERVIEW
This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling.
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 3, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 4.)
TDO - TEST DATA OUT (OUTPUT )
The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 3, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 4.)
PERFORMING A TAP RESE T
The TAP circuitry does not have a reset pin (TRST#, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and preloads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
DISABLING THE JTAG FEATUR E
It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device.
TEST ACCESS PORT (TAP) REGISTERS
OVERVIEW
The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins.
TEST ACCESS PORT (TAP )
TCK - TEST CLOCK (INPUT )
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.
TMS - TEST MODE SELECT (INPUT )
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
INSTRUCTION REGISTE R
The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the
TDI - TEST DATA IN (INPUT )
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is
May 22, 199 9
17
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path.
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM TAP CONTROLLER INSTRUCTION SET
OVERWIEW
There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables.
BYPASS REGISTE R
The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.
BOUNDARY SCAN REGISTE R
The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for x36 device and 51 bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit's position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state.
INDENTIFICATION (ID) REGISTE R
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into ShiftDR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon powerup and at any time the TAP controller is placed in the testlogic reset state.
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GALVANTECH, INC.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state.
1
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
TEST-LOGIC RESET 0
0
REUN-TEST/ IDLE
1
SELECT DR-SCAN 0
1
SELECT IR-SCAN 0 1 CAPTURE-IR 0
1
SAMPLE/PRELOA D
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device's input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command.
1
CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 1 0
SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
1
0
0
EXIT2-DR 1 UPDATE-DR 1 0
Note: The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Figure 3 TAP CONTROLLER STATE DIAGRAM
0
Bypass Register
2 1 0
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
TDI
Selection Circuitry
Instruction Register
31 30 29
... ...
Selection Circuitry
0
TDO
2
1
Identification Register
x
..
2
1
0
Boundary Scan Register*
TDI
RESERVED
Do not use these instructions. They are reserved for future use.
TDI
TAP CONTROLLER
*X = 70 for the x36 configuration; *X = 51 for the x18 configuration.
Figure 4 TAP CONTROLLER BLOCK DIAGRAM 19
Galvantech, Inc. reserves the right to change products or specifications without notice .
May 22, 199 9
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
TAP AC TEST CONDITIONS Input pulse levels Iutput rise and fall times Input timing reference levels Output reference levels Output load termination supply voltage VSS to 3.0V 1.5ns 1.5V 1.5V 1.5V
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM TAP OUTPUT LOAD S
TDO Z0 = 50 50 Vt = 1.5V Figure 5 TAP AC OUTPUT LOAD EQUIVALENT 20 pF
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITION S
(20oC Tj 110C; VCC = 3.3V -0.2V and +0.3V unless otherwise noted)
DESCRIPTIOP N
Input High (Logic 1) voltag e Input Low (Logic 0) Voltag e Input Leakage Curren t TMS and TDI input Leakage Current Output Leakage Curren t LVCMOS Output Low Voltag e LVCMOS Output High Voltag e LVTTL Output Low Voltag e LVTTL Output High Voltag e 0V < VIN < VCC 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100uA IOHC = 100uA IOLT = 8.0mA IOHT = 8.0mA
CONDITION S
SYMBO L
VIH VIl ILI ILI ILO VOLC VOHC VOLT VOHT
MIN
2.0 -0.3 -5.0 -30 -5.0
MAX
VCC + 0.3 0.8 5.0 30 5.0 0.2
UNITS
V V uA uA uA
NOTES
1, 2 1, 2
1, 3 1, 3 1 1
VCC - 0.2 0.4 2.4
NOTE:
1. 2. All voltages referenced to VSS (GND). Overshoot: VIH(AC) VCC + 1.5V for t tKHKH/2. Undershoot: VIL(AC) -0.5V for t tKHKH/2 Power-up: VIH +3.6V and VCC 3.135V and VCCQ 1.4V for t 200ms During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W#, ADV/LD#, etc.) may not have pulse widths less than tKHKL (MIN). This parameter is sampled.
3.
May 22, 199 9
20
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
t
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM TAP TIMING
tTHTH
THTL
t
TLTH
TEST CLOCK (TCK)
tMVTH tTHMX
TEST MODE SELECT (TMS)
tDVTH tTHDX
TEST DATA IN (TDI)
tTLQV tTLQX
TEST DATA OUT (TDO)
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (20oC Tj 110C; VCC = 3.3V -0.2V and +0.3V)
DESCRIPTIO N Clock
Clock cycle tim e Clock frequenc y Clock HIGH tim e Clock LOW tim e
t t t
SYM
MIN
MAX
UNITS
THTH
f
20 50 8 8 0 10 5 5 5 5 5 5
ns MHz ns ns ns ns ns ns ns ns ns ns
TF
THTL TLTH
Output Time s
TCK LOW to TDO unknow n TCK LOW to TDO vali d TDI valid to TCK HIG H TCK HIGH to TDI invali d
tTLQX tTLQV tDVTH tTHDX
Setup Time s
TMS setup Capture setup
tMVTH tCS
Hold Time s
TMS hold Capture hold
t
THMX
t
CH
NOTE:
1.
t
CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register .
2. Test conditions are specified using the load in Figure 5.
May 22, 199 9
21
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
IDENTIFICATION REGISTER DEFINITION S
INSTRUCTION FIELD REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) RESERVED (17:12) GALVANTECH JEDEC ID CODE (11:1) ID Register Presence Indicator (0) 256K x 36 XXXX 00110 00100 XXXXXX 00011100100 1 512K x 18 XXXX 00111 00011 XXXXXX 00011100100 1
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
DESCRIPTION Reserved for revision number . Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use . Allows unique identification of DEVICE vendor. Indicates the presence of an ID register.
SCAN REGISTER SIZE S
REGISTER NAM E BIT SIZE (x36 ) BIT SIZE (x18 )
Instruction Bypass ID Boundary Scan
3 1 32 70
3 1 32 51
INSTRUCTION CODE S
Instructio n EXTEST
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
Code Descriptio n 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant . 001 Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations . 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state . 011 Do not use these instructions; they are reserved for future use . 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device oper ations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant . 101 Do not use these instructions; they are reserved for future use . 110 Do not use these instructions; they are reserved for future use . 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations .
May 22, 199 9
22
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
BOUNDARY SCAN ORDER (256K x 36 )
BIT#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc NC DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE SA SA SA SA SA1 SA0 92 93 94 95 96 97 98 99 100 1 2 3 6 7 8 9 12 13 14 18 19 22 23 24 25 28 29 30 31 32 33 34 35 36 37 6B 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 1K 2L 2N 1P 3R 2C 3C 5C 6C 4N 4P
SINGAL NAME
SA SA SA SA SA SA SA DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA NC ADV/LD# OE# CKE# R/W# CLK
TQFP
44 45 46 47 48 49 50 51 52 53 56 57 58 59 62 63 64 68 69 72 73 74 75 78 79 80 81 82 83 84 85 86 87 88 89
BUMP ID
2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 7H 6G 6E 7D 6A 5A 4G 4A 4B 4F 4M 4H 4K
May 22, 199 9
23
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
BOUNDARY SCAN ORDER (512K x 18 )
BIT#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
DQb DQb DQb NC DQb DQb DQb DQb DQb MODE SA SA SA SA SA1 SA0 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
SINGAL NAME
SA SA SA SA SA SA SA DQa DQa DQa DQa ZZ DQa DQa DQa DQa DQa SA SA SA SA NC ADV/LD# OE# CKE# R/W# CLK CE2# BWa# BWb# CE2 CE# SA SA DQb
TQFP
44 45 46 47 48 49 50 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 87 88 89 92 93 94 97 98 99 100 8
BUMP ID
2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B 5L 3G 2B 4E 3A 2A 1D
May 22, 199 9
24
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
100 Pin TQFP Package Dimension s
16.00 + 0.10 14.00 + 0.10
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
May 22, 199 9
25
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
PRELIMINARY
GALVANTECH, INC.
7 x 17 (119-lead) BGA Dimension s
22.00 + 0.20 20.32
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
1.27
7 6
14.00 + 0.20
5
7.62 1.27
4 3 2 1
UT R P NML KJ
HGFEDCBA
o 0.75+0.15 (119X)
BOTTOM VIEW
19.50 + 0.10
12.00 + 0.10
0.70 REF.
0.90 + 0.10
30 TYP.
0.56 REF.
0.60 + 0.10
SIDE VIEW
Note: All dimensions in Millimeters
May 22, 199 9
26
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99
2.40 MAX.
PIN 1A CORNER
TOP VIEW
PRELIMINARY
GALVANTECH, INC.
Ordering Information for 256K x 36
GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM
GVT 71256ZC36 X - X
Galvantech Prefix Part Number Speed (5 = 5.0ns cycle/3.2ns access 6 = 6.0ns cycle/3.6ns access 7.5 = 7.5ns cycle/4.2ns access 10 = 10ns cycle/5.0ns access) Package (B = 119 BUMP PBGA, T = 100 PIN TQFP)
Ordering Information for 512K x 18 GVT 71512ZC18 X - X
Galvantech Prefix Part Number Speed (5 = 5.0ns cycle/3.2ns access 6 = 6.0ns cycle/3.6ns access 7.5 = 7.5ns cycle/4.2ns access 10 = 10ns cycle/5.0ns access) Package (B = 119 BUMP PBGA, T = 100 PIN TQFP)
May 22, 199 9
27
Galvantech, Inc. reserves the right to change products or specifications without notice .
Rev. 5/99

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